1) Field of the Invention
The present invention relates to a parasitic element extraction apparatus that extracts the parasitic element of a semiconductor integrated circuit.
2) Description of the Related Art
In recent years, following the development of the multilayer wiring and microfabrication in the manufacturing of semiconductors, there is a trend for making a gate mounted on one chip of a semiconductor integrated circuit large in scale to thereby acquire a semiconductor integrated circuit with one chip that has a high performance and is capable of performing advanced functions. Therefore, a logical design based on manual circuit diagram drawing is indispensable, and a circuit design according to a top-down design scheme using a hardware description language such as VHDL (Very high speed integrated circuit Hardware Description Language) or Verilog-HDL (Verilog Hardware Description Language) and a logical synthesis apparatus becomes common.
However, when the size of the semiconductor to be manufactured is 0.35 xcexcm or small, then a delay time caused by wirings increases more than the delay time of the transistors. As a result, with the design scheme of developing a design to a logical circuit by the logical synthesis apparatus based on the hardware description language described at functional level, creating a net list, and laying out the logical circuit by an automatic placement and routing apparatus, it is impossible to obtain a semiconductor integrated circuit that actually functions. In other words, a semiconductor integrated circuit that actually functions cannot be obtained when the semiconductor integrated circuit that has a minimum processing size in the manufacturing of semiconductors reduced to deep submicron is not designed in light of problems related to manufacturing techniques such as power supply distribution, signal integrity, and electro migration. Therefore, it is necessary to extract parasitic elements from a net list after the layout and to perform a circuit simulation.
Nevertheless, because of the large scale of the semiconductor integrated circuit, when parasitic elements are extracted from all the related nets to a net of interest independently of one another, the quantity of information becomes so large that it disadvantageously takes considerably long time to calculate delay after the extraction of the parasitic elements. In addition, when parasitic elements are extracted on the assumption that all the nets are equal in potential; accuracy in the delay calculation is disadvantageously deteriorated because of the difference between simulated operation and actual operation.
To solve this problem, according to the conventional art, for example, Japanese Patent Application Laid-Open No. 2002-41595 (hereinafter xe2x80x9cPatent Document 1xe2x80x9d), an active node the potential of which changes and an inactive node the potential of which does not change are extracted in executing a pre-layout simulation, thereby facilitating selecting a parasitic element extraction target node in layout pattern data.
However, a transistor has different delays between the rise and fall of a signal. Therefore, according to the conventional art of extracting the parasitic elements based only on whether a potential changes, accuracy in the delay calculation and signal integrity is disadvantageously deteriorated since the operation of the semiconductor integrated circuit in the simulation differs from the actual operation of the semiconductor integrated circuit.
It is an object of the present invention to solve at least the problems in the conventional technology.
The parasitic element extraction apparatus extracts parasitic elements based on logical netlist information that defines cell information for defining cells of a semiconductor integrated circuit and nets showing connection between the cells, layout information that defines position information on wiring patterns of the cells and the nets connecting the cells, the position information being used when placement and routing are carried out using the logical netlist information, and a library that defines capacitances and inductances for the wiring patterns.
The parasitic element extraction apparatus according to the present invention comprises a category classification unit that classifies the nets defined in the logical netlist information based on a constraint that defines at least two categories of a first category to a third category among five categories; and a parasitic element extraction unit that extracts the parasitic elements while attention is paid to any one of the capacitances and the inductances defined in the constraint for each of the classified nets, and generates connection information including the extracted parasitic elements.
The five categories are a first category related to the nets adjacent a net of interest among the nets defined in the logical netlist information and having potentials of the adjacent nets being likely to change in a same direction as a direction of the potential of the net of interest; a second category related to the nets adjacent the net of interest and having the potentials likely to change in an opposite direction to the direction of the potential of the net of interest; a third category related to the nets adjacent the net of interest and having the potentials likely to change in both the same direction and the opposite direction to the direction of the potential of the net of interest; a fourth category related to the nets having the potentials fixed even when logical of the semiconductor integrated circuit changes; and a fifth category related to the nets adjacent the net of interest that do not affect any one of the capacitance and the inductance for the net of interest or that can ignore any one of the capacitance and the inductance for the net of interest.
The other objects, features and advantages of the present invention are specifically set forth in or will become apparent from the following detailed descriptions of the invention when read in conjunction with the accompanying drawings.